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Intel has open up details on its new graphics chip named Larrabee which will compete head to head with GeForce and Radeon lines of video cards from NVIDIA and AMD/ATI respectively.

Some people may think of it as a GPU but it isn’t although it can perform various graphics functions. The main difference between other GPUs and Larrabee is that it is based on Intel x86 platform for its shader cores instead of a proprietary graphics-focused instruction set. Unlike current GPUs it will also feature cache coherency across all its cores like a multi-core CPU.

The number of cores in each Larrabee chip will vary from 8 to 48 depending on target market. The individual cores in Larrabee are derived from the Intel Pentium processor with added 64-bit instructions and multi-threading. Each core has 256 kilobytes of level-2 cache allowing the size of the cache to scale with the total number of cores.

The chip is due in 2009-2010.

Larrabee combines the best attributes of a central processing unit (CPU) with a graphics processor as described by Larry Seiler, a senior principal engineer in Intel’s Visual Computing Group:

The thing we need is an architecture that combines the full programmability of the CPU with the kinds of parallelism and other special capabilities of graphics processors. And that architecture is Larrabee.

A key characteristic of this vector processor is a property called “being vector complete” which means it can run 16 pixels in parallel, 16 vertices in parallel, or 16 more general program indications in parallel.

Some of the salient features of Larrabee are:

• Larrabee programming model
  This enables development of graphics APIs, rapid innovation of new graphics algorithms, and true general purpose computation on the graphics processor with established PC software development tools.
• Software-based scheduling
  Larrabee features task scheduling which is performed entirely with software, rather than in fixed function logic. Due to this resource scheduling can be adjusted based each workload’s unique computing demand.
• Ring network
  Larrabee uses a 1024 bits-wide, bi-directional ring network (i.e., 512 bits in each direction) to allow agents to communicate with each other in low latency manner resulting in super fast communication between cores
• Execution threads
  Larrabee architecture supports four execution threads per core with separate register sets per thread. This allows the use of a simple efficient in-order pipeline, but retains many of the latency-hiding benefits of more complex out-of-order pipelines when running highly parallel applications.